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DM9301FP 100mbps ethernet fiber/twisted pair single chip media converter final 1 version: DM9301FP-ds-f03 june 06, 2007 general description the DM9301FP is a physical-layer, single-chip, low- power media converter for 100base-tx/fx full duplex repeater applications. on the tx media side, it provides a direct interface to unshielded twisted pair cable 5 (utp5) for 100base-tx fast ethernet. on the fx media side, it provides a direct interface to a pseudo emitter coupled logic level interface (pecl). the DM9301FP uses a low power and high performance cmos process. it contains the entire physical layer functions of 100base-tx as defined by ieee802.3u, including the physical coding sublayer (pcs), physical medium attachment (pma), twisted pair physical medium dependent sublayer (tp-pmd) and a pecl compliant interface for a fiber optic module, compliant with ansi x3.166. the DM9301FP provides two independent clock recovery circuits to minimize bit delay through the converter (no fifo is used to buffer data between the fx and tx interfaces). furthermore, due to the excellent rise/fall time control by a built-in wave- shaping filter, the DM9301FP needs no external filter to transport signals to the media on the 100base-tx interface. patent-pending circuits ? smart adaptive receiver equalizer ? digital algorithm for high frequency clock/data recovery circuit ? high speed wave-shaping circuit block diagram tx code- group alignment monitor descrambler serial to parallel nrzi to nrz rx crm mlt-3 to nrzi adaptive eq cgm 125m tprxclk 25m tprxclk 25m osc/xtal tprxi+/- parallel to serial fx code- group alignment monitor serial to parallel rx crm scrambler parallel to serial nrz to nrzi nrzi to mlt-3 mlt-3 driver tptxo+/- rise/fall time ctl 25m fxrxclk 125m fxrxclk pecl txmt pecl rcvr peclrxi +/- pecltxo +/- fxsd rcvr link status monitor & led driver peclsd nrz to nrzi nrzi to nrz
DM9301FP 100mbps ethernet fiber/twisted pair single chip media converter 2 final version: DM9301FP-ds-f03 june 06, 2007 table of contents general description.................................................. 1 block diagram .......................................................... 1 table of contents...................................................... 2 features ................................................................... 3 pin configuration: DM9301FP qfp ......................... 4 pin description ......................................................... 5 functional description............................................ 10 100base-fx to tx operation ................................. 10 ? fx pecl receiver.............................................. 10 ? fx receiver clock recovery module................. 10 ? fx nrzi to nrz converter ................................ 10 ? fx serial to parallel converter ........................... 11 ? fx code group alignment monitor .................... 11 ? tx scrambler...................................................... 11 ? tx parallel to serial converter ........................... 11 ? tx nrz to nrzi converter ................................ 11 ? tx nrzi to mlt-3 converter ............................. 11 ? tx mlt-3 driver ................................................. 11 100base-tx to fx operation ................................. 12 ? tx signal detect................................................. 12 ? tx digital adaptive equalization ........................ 12 ? tx mlt-3 to nrzi decoder................................ 13 ? tx clock recovery module ................................ 13 ? tx nrzi to nrz decoder................................... 13 ? tx serial to parallel converter ........................... 13 ? tx code group monitor...................................... 13 ? tx descrambler.................................................. 13 ? fx parallel to serial converter........................... 13 ? fx nrz to nrzi encoder................................... 13 ? link monitor and led driver .............................. 13 absolute maximum ratings ................................... 14 dc electrical characteristics.................................. 15 ac electrical characteristics.................................. 16 timing waveforms ................................................. 17 ? 100base-tx to fx transmit timing diagram... 17 ? 100base-fx to tx transmit timing diagram... 17 ? 5-bit symbol 100base-tx/fx transmit timing diagram............................................................... 17 ? 5-bit symbol 100base-tx/fx receive timing diagram............................................................... 18 application circuit (for reference only) ............... 19 package information .............................................. 21 ordering information .............................................. 22 disclaimer............................................................... 22 company overview................................................ 22 products ................................................................. 22 contact windows ................................................... 22 warning .................................................................. 22
DM9301FP 100mbps ethernet fiber/twisted pair single chip media converter final 3 version: DM9301FP-ds-f03 june 06, 2007 features ? 100base-tx/fx single-chip media converter ? total bit delay from fx to tx interface is 20 bit times (10 bit times each direction). ? optional propagate halt on no link condition ? compliant with ieee802.3u 100base-tx standard ? compliant with ansi x3t12 tp-pmd 1995 standard ? compliant with ansi x3.166 fddi-pmd ? supports half and full duplex operation 100mbps, the DM9301FP operates in full duplex mode at all times ? high performance 100mbps clock generator and data recovery circuit ? controlled output edge rates in the 100base-tx transmitter without the need for an external filter ? led supports for fx link, tx link, fx receive data; tx receives data, and fx code group error and tx code group error. ? built in led test, all led will light during a reset condition on the DM9301FP ? digital clock recovery and regeneration circuit using an advanced digital algorithm to minimize jitter ? supports diagnostic tx to tx analog loopback and fx to fx analog loopback (loopback at the nrzi interface) ? supports diagnostic tx to tx digital loopback and fx to fx digital loopback (loopback at the 5b symbol interface) ? low-power, high-performance cmos process ? available in a 100 qfp package
DM9301FP 100mbps ethernet fiber/twisted pair single chip media converter 4 final version: DM9301FP-ds-f03 june 06, 2007 pin configuration: DM9301FP qfp avcc peclsd- peclrxi- peclrxi+ agnd avcc pecltxo- pecltxo+ agnd tprxi- agnd avcc avcc agnd agnd agnd tptxo- tptxo+ avcc osc/x1 x2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 28 30 27 29 80 79 78 77 76 75 74 72 73 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 tpo1 tpo2 tpo3 tpo4 tpo5 tpo6 dvcc dgnd tridrv fxerrled# fxrcvled# dgnd txalpbk txerrled# txrcvled# txlnkled# tpi0 tpi1 tpi2 tpi3 dgnd tpmux 50 49 48 47 46 45 44 43 42 40 41 39 38 37 36 35 34 33 32 31 tpen dvcc txd0 txd1 txd2 frcfxsd txd3 txd4 txclk hltnolnk dvcc dgnd dgnd bgret bgref osc/xtl# agnd 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 agnd agnd rxd4 dvcc dvcc tpo0 dgnd DM9301FP tprxi+ reset# rxd0 dgnd dvcc rxd2 rxd3 dgnd rxclk configa configb fxdlpbk txdlpbk dvcc fxlnkled# fxalpbk dgnd muxctl1 muxctl0 bpscram rxd1 avcc avcc agnd avcc agnd peclsd+ testmode dgnd dvcc dvcc dgnd dgnd
DM9301FP 100mbps ethernet fiber/twisted pair single chip media converter final 5 version: DM9301FP-ds-f03 june 06, 2007 pin description pin no. pin name i/o description media interface 1, 2 tprxi+, tprxi- i 100mbps-tx differential input pair: these pins are differential receive input for 100base- tx. they are capable of receiving 100base-tx mlt-3 data. 13, 14 tptxo-, tptxo+ o 100base-tx differential output pair: these outputs drive mlt-3 encoded data over 100mbps twisted pair cable and provide controlled rise and fall times designed to filter the transmitter output, reducing any associated emi. 24, 25 peclrxi-, peclrxi+ i 100base-fx pecl receive data differential pair: these pins are differential receive input for 100base- fx pecl. they are capable of receiving pecl 100base-fx nrzi data. 18, 19 pecltxo-, pecltxo+ o 100base-fx transmit differential output pair: these outputs drive nrzi encoded data for pecl fx interface. 22, 23 peclsd-, peclsd+ i 100base-fx pecl signal detect: these pins are differential signals that indicate to the DM9301FP that the optical module interface is detecting valid optical energy. clock and misc. interface 27 osci/x1 i crystal or oscillator input: this pin should connect to one side of a 25mhz, 50ppm crystal if osc/xtl#=0. this pin is the 25mhz, 50ppm external ttl oscillator input, if osc/xtlb=1. 28 x2 o crystal oscillator output: the other side of a 25mhz, 50ppm crystal should connect to this pin if osc/xtl#=0. leave this pin open if osc/xtl#=1. 30 osc/xtl# i crystal or oscillator selector pin: osc/xtl#=0: an external 25mhz, 50ppm crystal should connect to x1 and x2 pins. osc/xtl#=1: an external 25mhz, 50ppm oscillator should connect to x1 and left x2 pin open. 8 bgref i bandgap voltage reference resistor: it connects to a 6.49k ? , 1% error tolerance resistor between this pin and bgret pin 9 to provide an accurate current reference for the chip. 9 bgret i bandgap return return pin for 6.49k ? resistor connection, do not connect to ground.
DM9301FP 100mbps ethernet fiber/twisted pair single chip media converter 6 final version: DM9301FP-ds-f03 june 06, 2007 clock and misc. interface (continued) 84 tridrv i tristate digital output pins: when set high, all digital output pins are set to high impedance. 85 reset# i reset: active low input that initializes the DM9301FP, must be asserted low for 30msecs after vcc is stable. 34 hltnolnk i send halt on no link condition: causes the DM9301FP to send out a halt symbol to the tx interface if no fx link active or send out a halt symbol to the fx interface if no tx link active. propagates a no-link condition to the link partner if 1, idle symbol if 0. active high 93 configa i config a: must be connected to gnd 95 configb i config b: must be connected to gnd led interface 67 fxlnkled# od fx link led: indicates good link status for 100mbps fx operation. active low (open drain output) 64 txlnkled# od tx link led: indicates good link status for 100mbps tx operation. active low (open drain output) 69 fxrcvled# od fx receive led: indicates the presence of receive activity for 100mbps fx operation. active low (open drain output) the DM9301FP incorporates a "monostable" function on the fxrcvled output. this ensures that even minimum size packets generate adequate led on to insure visibility. 62 txrcvled# od tx receive led: indicates the presence of receive activity for 100mbps tx operation. active low (open drain output) the DM9301FP incorporates a "monostable" function on the txrcvled output. this ensures that even minimum size packets generate adequate led on to insure visibility. 80 fxerrled# od fx error led: indicates an error was detected by the fx code group alignment monitor function on the fx receiver. active low (open drain output) the DM9301FP incorporates a "monostable" function on the fxerrled output. this ensures that even minimum size errors generate adequate led on to insure visibility.
DM9301FP 100mbps ethernet fiber/twisted pair single chip media converter final 7 version: DM9301FP-ds-f03 june 06, 2007 led interface(continued) 52 txerrled# od tx error led: indicates an error was detected by the tx code group alignment monitor function on the tx receiver. active low (open drain output) the DM9301FP incorporates a "monostable" function on the txerrled output. this ensures that even minimum size errors generate adequate led on to insure visibility. diagnostic port interface 36 fxalpbk i fx interface analog loop back: loops the fx nrzi analog transmit data path to the fx nrzi analog receive path. initiated at an h/w reset. active high. 35 txalpbk i tx interface analog loop back: loops the tx nrzi analog transmit data path to the tx nrzi analog receive path. initiated at an h/w reset. active high. 96 fxdlpbk i fx interface digital loop back: loops the fx 5-bit symbol digital transmit data path to the fx 5-bit symbol digital receive path. initiated at an h/w reset. active high. 97 txdlpbk i tx interface digital loop back: loops the tx 5-bit symbol digital transmit data path to the tx 5-bit symbol digital receive path. initiated at an h/w reset. active high. 79, 77, 76, 74, 73 rxd0, rxd1, rxd2, rxd3, rxd4 0 receive data 4 through 0: the receive data 5-bit symbol interface. data is clocked out on the falling edge of rxclk. 70 rxclk o receive clock: 25 mhz recovered clock, clock source is selected by the muxctl1 and muxctl0. 48, 47, 45, 44, 43 txd0, txd1, txd2, txd3, txd4 i transmit data 4 through 0: the transmit data 5-bit symbol interface. data is clocked in on the rising edge of txclk. 71 txclk o transmit clock: 25 mhz recovered clock, clock source is selected by the muxctl1 and muxctl0.
DM9301FP 100mbps ethernet fiber/twisted pair single chip media converter 8 final version: DM9301FP-ds-f03 june 06, 2007 diagnostic port interface (continued) 39, 40 muxctl1, muxctl0 i mux. control 1 and 0: used for testing the DM9301FP data paths. set to zero for normal operation. initiated at an h/w reset. active high. muxctl1 muxctl0 data path 0 0 normal, fx to tx and tx to fx 1 0 tx transmit from txd[4:0] txclk from tx pll tx receive to rxd[4:0] rxclk from tx receive clock 0 1 fx transmit from txd[4:0] txclk from fx pll fx receive to rxd[4:0] rxclk from fx receive clock 1 1 tx transmit from txd[4:0] txclk from tx pll fx receive to rxd[4:0] rxclk from fx receive clock 65, 54, 55, 57, 58, 60, 61 tpo6, tpo5, tpo4, tpo3, tpo2, tpo1, tpo0 o test port output: reflects the DM9301FP internal status. selection of status indicators is made by using tpen and tpmux. initiated at an h/w reset. active high. 92, 91, 89, 88 tpi3, tpi2, tpi1, tpi0, i test port input: controls the DM9301FP internal test features. selection of input control is made by using tpen and tpmux. tpen must be true (one) for this signal to take effect. initiated at an h/w reset. active high.
DM9301FP 100mbps ethernet fiber/twisted pair single chip media converter final 9 version: DM9301FP-ds-f03 june 06, 2007 diagnostic port interface (continued) 49 frcfxsd i force fx signal detect forces the DM9301FP fx interface signal detect true initiated at an h/w reset. active high. 38 tpen i test port enable: enables the DM9301FP test port features. initiated at an h/w reset. active high. 87 tpmux i test port mux: controls the DM9301FP test port input and output bits. a value of zero indicates the tx interface and a value of one indicates the fx interface. tpen must be true (one) for this signal to take effect. initiated at an h/w reset. active high. 41 bpscram i bypass scrambler: controls the DM9301FP tx interface scrambler/de - scrambler function. a value of zero indicates to scramble and de-scramble the tx interface 5 -bit symbol data to and from the fx interface. a value of one bypasses the scrambler/de-scrambler function. initiated at an h/w reset. active high. power and ground pins : the power (vcc) and ground (gnd) pins of the DM9301FP are grouped in pairs of two categories - digital circuitry power/ground pairs and analog circuitry power/ground pair. group a - digital supply pairs 33, 42, 50, 53, 63, 68, 72, 78, 82, 90, 98 dgnd p digital logic ground. 37, 46, 51, 56, 66, 75, 81, 86, 94 dvcc p digital logic power supply group b - analog circuit supply pairs 5, 6, 11, 12, 16, 17, 20, 29, 32, 99, 100, agnd p analog circuit ground 3, 4, 7, 10, 15, 21, 26, 31 avcc p analog circuit power supply
DM9301FP 100mbps ethernet fiber/twisted pair single chip media converter 10 final version: DM9301FP-ds-f03 june 06, 2007 functional description the DM9301FP fast ethernet single-chip tx/fx media converter, provides the functionality as specified in ieee802.3, integrates the complete 100base-tx and a pecl optic module interface for 100base-fx. the DM9301FP implements the pcs, pma, and tp-pmd sublayer functions, as defined by specification. the term ?x? will be used to describe the sections used in the fiber phy layer interface. the term ?x? will be used to describe the sections used in the twisted-pair pmd layer interface. 100base-fx to tx operation the block diagram in figure 1 provides an overview of the functional blocks contained in the fx to tx media converter interface. the fx to tx interface includes the following functional blocks: ? fx pecl receiver ? fx receiver clock recovery module ? fx nrzi to nrz converter ? fx serial to parallel converter ? fx code group alignment monitor ? tx scrambler ? tx parallel to serial converter ? tx nrz to nrzi converter ? tx nrzi to mlt-3 converter ? tx mlt-3 driver fx pecl receiver the pecl receiver receives nrzi encoded, differential pseudo emitter coupled logic level signal. the receiver converts the receive signal into a single-ended nrzi signal and presents this signal to the fx clock recovery module. fx receiver clock recovery module the fx clock recovery module accepts nrzi data from the pecl receiver. the fx clock recovery module locks onto the data stream, using a phase lock loop (pll) and extracts the 125 mhz reference clock. the extracted and synchronized clock and data are presented to the fx nrzi to nrz decoder. fx nrzi to nrz converter the receive data stream is required to be nrzi encoded for compatibility with the standards for 100base- fx. this conversion process must be reversed on the transmit end. the fx nrzi to nrz decoder receives the nrzi data stream from the fx clock recovery module and converts it to a nrz data stream to be presented to the fx serial to parallel conversion block. cgm 25m osc/xtal fx code- group alignment monitor fx serial to parallel fx rx crm tx scrambler tx parallel to serial tx nrz to nrzi tx nrzi to mlt-3 mlt-3 driver tptxo+/- rise/fall time ctl 25m fxrxclk 125m fxrxclk fx pecl rcvr peclrxi +/- fxsd rcvr fx link status monitor peclsd fx nrzi to nrz fx to tx block diagram figure 1
DM9301FP 100mbps ethernet fiber/twisted pair single chip media converter final 11 version: DM9301FP-ds-f03 june 06, 2007 fx serial to parallel converter the serial to parallel converter receives a serial data stream from the nrzi to nrz converter, and converts the data stream to parallel data to be presented to the scrambler. the parallel data format presented to the tx scrambler is 5b coded. fx code group alignment monitor the fx code group alignment block receives non- aligned 5b data from the fx serial to parallel converter and monitors it for 5b code group violations. fx code group alignment occurs after the j/k is detected, and subsequent data is monitored on a fixed boundary. if a violation is detected, the fx code group alignment monitor block signals the error to the link status monitor blocks. in turn, the link status monitor block flashes the fx error led (fxerrled#). tx scrambler the scrambler also receives data from the fx serial to parallel converter. data from the serial to parallel conversion block is 5b symbol encoded. the scrambler is required to control the radiated emissions (emi) by spreading the transmit energy across the frequency spectrum at the media connector and on the twisted pair cable in 100base- tx transmit operation. by scrambling the data, the total energy presented to the cable is randomly distributed over a wide frequency range. without the scrambler, energy levels on the cable could peak beyond fcc limitations at frequencies related to repeated 5b sequences like continuous transmission of idle symbols. the scrambler outp ut is combined with the nrz 5b data from the fx serial to parallel converter via an xor logic function. the result is a scrambled data stream with sufficient randomization to decrease radiated emissions at critical frequencies. tx parallel to serial converter the tx parallel to serial converter receives parallel 5b scrambled data from the scrambler and serializes it (converts it fr om a parallel to a serial data stream). the serialized data stream is then presented to the nrz to nrzi converter block tx nrz to nrzi converter after the transmit data stream has been scrambled and serialized, the data must be nrzi encoded for compatibility with the tp-pmd standard for 100base-tx transmission over category-5 unshielded twisted pair cable. tx mlt-3 converter the mlt-3 conversion is accomplished by converting the data stream output from the nrzi encoder into two binary data streams with alternately phased logic one events. tx mlt-3 driver the two binary data streams created at the mlt-3 converter are fed to the twisted pair output driver which converts these streams to current sources and alternately drives either side of the transmit transformer primary winding resulting in a minimal current mlt-3 signal.
DM9301FP 100mbps ethernet fiber/twisted pair single chip media converter 12 final version: DM9301FP-ds-f03 june 06, 2007 100base-tx to fx operation the block diagram in figure 2 provides an overview of the functional blocks contained in the tx to fx media converter interface. the tx to fx interface contains the following functional blocks: ? tx digital adaptive equalization ? tx mlt-3 to nrzi ? tx clock recovery module ? tx nrzi to nrz decoder ? tx serial to parallel conversion ? tx descrambler ? tx code group alignment monitor ? fx parallel to serial conversion ? fx nrz to nrzi ? fx pecl transmitter tx signal detect the signal detects function meets the specifications mandated by the ansi xt12 tp-pmd100base-tx standards for both voltage thresholds and timing parameters. tx digital adaptive equalization when transmitting data at high speeds over copper twisted pair cable, attenuation based on frequency becomes a concern. in high speed twisted pair signaling, the frequency content of the transmitted signal can vary greatly during normal operation based on the randomness of the scrambled data stream. this variation in signal attenuation caused by frequency variations must be compensated for to ensure the integrity of the received data. in order to ensure quality transmission when employing mlt-3 encoding, the compensation must be able to adapt to various cable lengths and cable types depending on the installed environment. the selection of long cable lengths for a given implementation requires significant compensation which will be over-kill in a situation that includes shorter, less attenuating cable lengths. conversely, the selection of short or intermediate cable lengths requiring less compensation will cause serious under-compensation for longer length cables. tx code- group alignment monitor tx descrambler tx serial to parallel tx nrzi to nrz tx crm tx mlt-3 to nrzi tx adaptive eq cgm 125m tprxclk 25m tprxclk 25m osc/xtal tprxi+/- fx parallel to serial tx pecl txmt pecltxo +/- tx link status monitor tx nrz to nrzi tx to fx block diagram figure 2
DM9301FP 100mbps ethernet fiber/twisted pair single chip media converter final 13 version: DM9301FP-ds-f03 june 06, 2007 therefore, the compensation or equalization must be adaptive to ensure proper conditioning of the received signal independent of the cable length. tx mlt-3 to nrzi decoder the DM9301FP decodes the mlt-3 information from the tx digital adaptive equalizer into nrzi data. tx clock recovery module the tx clock recovery module accepts nrzi data from the mlt-3 to nrzi decoder. the tx clock recovery module locks onto the data stream and extracts the 125 mhz reference clock. the extracted and synchronized clock and data are presented to the nrzi to nrz decoder. tx nrzi to nrz decoder the tx transmit data stream is required to be nrzi encoded in for compatibility with the tp-pmd standard for 100base-tx transmission over category-5 unshielded twisted pair cable. this conversion process must be reversed on the receive end. the nrzi to nrz decoder receives the nrzi data stream from the tx clock recovery module and converts it to a nrz data stream to be presented to the tx seria l to parallel conversion block. tx serial to parallel converter the tx serial to parallel converter receives a serial data stream from the tx nrzi to nrz decoder, and converts the data stream to parallel data to be presented to the tx descrambler. the parallel data format presented to the tx descrambler is 5b coded. tx code group monitor the tx code group alignment block receives non- aligned 5b data from the tx descrambler and monitors it for 5b code group violations. tx code group alignment occurs after the j/k is detected, and subsequent data is monitored on a fixed boundary. if a violation is detected, the tx code group monitor block signals the error to the link status monitor block. in turn, the link status monitor block flashes the tx error led (txerrled#). tx descrambler because of the scrambling process required to control the radiated emissions of transmit data streams, the receiver must descramble the receive data streams. the tx descrambler receives scrambled parallel data streams from the serial to parallel converter, descrambles the data streams, and presents the data streams to the code group alignment block. fx parallel to serial converter the fx parallel to serial converter receives parallel 5b data from the tx de-scrambler and serializes it (converts it from a parallel to a serial data stream). the serialized data stream is then presented to the fx nrz to nrzi encoder block fx nrz to nrzi encoder after the transmit data stream has been serialized, the data must be nrzi encoded for compatibility with the standard for 100base-fx. link monitor and led driver the link monitor block monitors both the tx and fx interfaces for link active, receive data and erring 5-bit stream. the link monitor has the ability to detect each interfaces link status. the tx will transmit either an idle symbol or a halt symbol if the fx link is not established. conversely the fx will transmit either an idle symbol or a halt sy mbol if the tx link is not established. when an o link? condition exists, the interface pin called ltnolnk? will cause halt symbols to be transmitted instead of idle symbols. the link active led is a static indication of the tx and fx links. it will be true to indicate the presence of a link. the receive data and error led are generated through a ne-shot? so that even the smallest receive or error condition will be indicated.
DM9301FP 100mbps ethernet fiber/twisted pair single chip media converter 14 final version: DM9301FP-ds-f03 june 06, 2007 absolute maximum ratings* absolute maximum ratings (25 c) symbol parameter min. max. unit conditions v cc ma x . supply voltage -- 7.0 v non-operating v in dc input voltage (v in ) -0.5 5.5 v v out dc output voltage(v out ) -0.5 5.5 v tstg storage temperature rang (tstg) -65 +150 c pd power dissipation (pd) --- 1 w lt lead temp. (tl, soldering, 10 sec.) --- 240 c esd esd rating (rzap=1.5k,czap=100pf ) --- 4000 v operating conditions symbol parameter min. max. unit conditions dv cc ,av cc supply voltage 4.75 --- 5.25 tc case temperature 0 85 c pd (power dissipation) 100base-tx --- 200 ma 5v *comments stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only. functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DM9301FP 100mbps ethernet fiber/twisted pair single chip media converter final 15 version: DM9301FP-ds-f03 june 06, 2007 dc electrical characteristics (v cc = 5v) symbol parameter min. typ. max. unit conditions ttl inputs (dplxsel, reset# ) v il input low voltage 0.8 v i il = -400ua v ih input high voltage 2.0 v i ih = 100ua i il input low current -200 ua v in = 0.4v i ih input high current 100 ua v in = 2.7v led driver outputs (fxlinkled#, txlinkled#, fxrxd#,rxrxd#) v ol output low voltage 0.4 v i ol = 8ma v oh output high voltage 2.4 v i oh = -0.1ma tptx receiver v icm rxi+/rxi- input common-mode voltage 1.5 2.0 2.5 v 100 ? termination across tptx transmitter itd100 100txo+/- 100base-tx mode differential output current 19 20 21 ma pecl fx transmitter ifd100 pecltx+/- 100base-fx mode differential output current 19 20 21 ma v oh pecl output voltage ? high vcc- 1.05 vcc- 0.88 v v ol pecl output voltage ? low vcc- 1.81 vcc- 1.62 v
DM9301FP 100mbps ethernet fiber/twisted pair single chip media converter 16 preliminary version: DM9301FP-ds-f03 june 06, 2007 ac electrical characteristics (over full range of operating condition unless specified otherwise) symbol parameter min. typ. max. unit conditions transmitter t tr/f 100txo+/- differential rise/fall time 3.0 5.0 ns t tm 100txo+/- differential rise/fall time mismatch -0.5 0.5 ns t tdc 100txo+/- differential output duty cycle distortion -0.5 0.5 ns t t/t 100txo+/- differential output peak-to- peak jitter 300 ps x ost 100txo+/- differential voltage overshoot 5 % pecl transmitter (fx transmit interface) pt tr/f 100fxtd+/- differential rise/fall time 1.0 2.0 ns pt tm 100fxtd+/- differential rise/fall time mismatch -0.5 0.5 ns pt tdc 100fxtd+/- differential output duty cycle distortion -0.5 0.5 ns pt ppj 100fxtd+/- differential output peak-to- peak jitter 300 ps pt ddj 100fxtd+/- differential output data dependent jitter 2.0 ns clock specifications x ntol tx input clock frequency tolerance (oscillator or crystal input frequency) -50 +50 ppm 25mhz frequency x btol tx output clock frequency tolerance -100 +100 ppm 25mhz frequency t pwh osc pulse width high 14 ns t pwl osc pulse width low 14 ns t rpwh rx_clk pulse width high 14 ns t rpwl rx_clk pulse width low 14 ns
DM9301FP 100mbps ethernet fiber/twisted pair single chip media converter final 17 version: DM9301FP-ds-f03 june 06, 2007 timing waveforms 100base-tx to fx transmit timing diagram tprxi+/- t fx pd pecltx+/- 100base-tx to fx transmit timing parameters symbol parameter min. typ 1 . max. unit conditions t fx pd tprxi+/- to pecltx+/- out (fx latency) - - 10 bt 100base-fx to tx transmit timing diagram tprxi+/- t tx pd pecltx+/- 100base-fx to tx transmit timing parameters symbol parameter min. typ 1 . max. unit conditions t tx pd peclrx+/- to tptxo+/- out (tx latency) - - 10 bt 5-bit symbol 100base-tx/fx transmit timing diagram txclk t tx h t tx s t txd pdtpo txd [4:0] 100tx+/- t tx rft t txd pdfxo 100fx+/-
DM9301FP 100mbps ethernet fiber/twisted pair single chip media converter 18 preliminary version: DM9301FP-ds-f03 june 06, 2007 5-bit symbol 100base-tx/fx transmit timing parameters symbol parameter min. typ. 1 max. unit conditions t tx s txd[4:0] setup to tx_clk high 11 - - ns t tx h txd[4:0] hold from tx_clk high 0 - - ns t txd pdtpo txd[4:0] sampled to tptxo (txd to tp latency) - - 6 bt t txd pdfxo txd[4:0] sampled to pecltxo (txd to fx latency) - - 4 bt t tx r/f 100tx driver rise/fall time 3 4 5 ns 90% to 10%, into 100ohm differential 1 . typical values are at 25and are for design aid only; not guaranteed and not subject to production testing. 5-bit symbol 100base-tx/fx receive timing diagram rxclk rxd [4:0] tx rxi+/- t rx s t rx h fx rxi+/- t rxd pdtxi t rxd pdfxi 5-bit symbol 100base-tx/fx receive timing parameter symbol parameter min. typ 1 . max. unit conditions t rx s rxd[4:0) setup to rx_clk high 10 - - ns t rx h rxd[4:0]hold from rx_clk high 10 - - ns t rxd pdtxi txrxi in to rxd[0:3] out (rx latency) - - 6 bt t rxd pdfxi peclrdi in to rxd[4:0] out (rx latency) - - 4 bt
DM9301FP 100mbps ethernet fiber/twisted pair single chip media converter final 19 version: DM9301FP-ds-f03 june 06, 2007 mii application circuit: DM9301FP qfp (for reference only)
DM9301FP 100mbps ethernet fiber/twisted pair single chip media converter 20 preliminary version: DM9301FP-ds-f03 june 06, 2007 mii application circuit: DM9301FP qfp (for reference only) dm9301.dsn 1.1 9301 media converter custom 11 monday , april 24, 2000 davicom semiconductor, inc. tit le size document number rev date: sheet of gnd vcc gnd gnd gnd gnd gnd gnd vcc gnd gnd vcc vcc gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd peclsd+ peclrxi- peclrxi+ gnd gnd vcc vcc_t vcc_r vcc_t gnd pecltxo- pecltxo+ tptxo+ tpr xi + tpr xi - tptxo- vcc_t 3.3v vcc peclsd+ peclrxi- peclrxi+ 3.3v bfref tpo3 fxlnkled# tptxo+ tprxi- peclsd- gnd vcc gnd gnd rxd0 vcc peclsd- vcc tpo0 gnd rxd3 gnd tpo5 gnd txlnkled# vcc vcc gnd gnd gnd rxd2 gnd tptxo- peclrxi- gnd peclsd+ gnd vcc gnd gnd vcc x2 peclsd+ rxd4 vcc osc/x1 gnd vcc gnd vcc hltnolnk vcc txerrled# gnd gnd bfret gnd tpo1 vcc peclrxi- peclrxi+ gnd gnd tpo2 peclrxi+ vcc tpo6 gnd gnd gnd tprxi+ txclk rxclk gnd vcc vcc rxd1 gnd vcc gnd gnd gnd fxrcvled# tpo4 gnd pecltxo- pecltxo- pecltxo+ pecltxo+ vcc vcc txrcvled# fxerrled# reset# vcc_r vcc_r vcc vcc bpscram vcc gnd gnd gnd vcc vcc r14 49.9 1% r7 75 1% rj45 j1 1 2 3 4 5 6 7 8 c10 10uf smd-b c5 .1uf /1kv r8 75 1% r27 130/83 c24 .1uf r25 82/ 127 r9 75 1% r29 374/19.8k r10 75 1% u2 pe68515 8 7 6 5 4 3 2 1 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 116 15 14 13 12 11 10 9 470 ohm r6 d6 c9 10uf smd-b r18 49.9 1% d3 r16 49.9 1% c8 .1uf r15 6.49k 1% r17 49.9 1% 470 ohm r3 r21 300/ 182 r19 300/ 182 fx2 hfbr5103t 1 2 3 4 5 6 7 8 9 r22 62/ 69.8 r20 62/ 69.8 c23 .1uf dm9301f (tco) u1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 32 99 100 31 tprxi+ tprxi- avcc avcc agnd agnd avcc bgref bgret avcc agnd agnd tptxo- tptxo+ avcc agnd agnd pecltxo- pecltxo+ agnd avcc peclsd- peclsd+ peclrxi- peclrxi+ avcc osc/x1 x2 agnd osc/xtl# dgnd hltnolnk txalpbk fxalpbk dvcc tpen mu xc tl1 mu xc tl0 bpscram dgnd txd 4 txd 3 txd 2 dvcc txd 1 txd 0 frcfxsd dgnd dvcc txerrled# dgnd tpo5 tpo4 dvcc tpo3 tpo2 dgnd tpo1 tpo0 txrcvled# dgnd txlnkled# tpo6 dvcc fxlnkled# dgnd fxrcvled# rxclk txclk dgnd rxd4 rxd3 dvcc rxd2 rxd1 dgnd rxd0 fxerrled# dvcc dgnd testmode tridr v reset# dvcc tpmux tpi0 tpi1 dgnd tpi2 tpi3 configa dvcc configb fxdlpbk txdlpbk dgnd agnd agnd agnd avcc c16 .1uf c15 .1uf l4 1uh l3 1uh c26 .1uf c25 .01uf c27 .01uf c11 .1uf s1 sw pushbutton r23 130/13.2k c4 .1uf c17 .01uf c18 .1uf c21 .01uf c19 .01uf c20 .1uf c22 .1uf r26 82/127 r12 0 ohm r13 0 ohm l1 ferrite hi current j? con4 1 2 3 4 j? con4 1 2 3 4 l2 ferrite hi current c12 .1uf c29 .1uf c28 .01uf c14 18pf 470 ohm r2 d2 3.3v sot-223 800ma u3 3 1 2 vin gnd vout d1 470 ohm r1 c2 .1uf c3 .01uf c1 10uf smd-b r28 130/ 83 470 ohm r4 led d4 j2 power jack c6 .1uf d5 470 ohm r5 r30 130 /83 r24 82/ 127 fx1 v23818-c8-v10 1 2 3 4 5 6 7 8 9 c7 10uf smd-b y1 25m c13 18pf r11 10k plus 5 volt d.c. input locate near u1's vcc & ground pins physically place caps on solder side. digital ckt power & ground area tx ckt power/ground area bypass capacitor for u1 place caps close to u1 pins halt if no link place these components as close to optics as possible. both leds in one package. d2 is upper led (txlnk) load only r12 or r13 r12=+5v for hfbr large optic r13=3.3v for siemans v23812 optic. disable scrambler isolation barrier. no power under this area. all these components and their traces should not intersect other areas. this node will be 3.3v or 5v depending on strapping. r19 182 300 r20 69.8 62 r21 182 300 r22 69.8 62 r23 13.2k 130 r24 127 82 optic fx1 fx2 u3 in out c10 in out c11 in out r25 127 82 r26 127 82 r12 out 0 r13 0 out r27 83 130 r28 83 130 r29 19.8k 374 r30 83 130 pop table for : 3.3v 5.0v place caps close to u1 pins load only for 3.3v siemans v23812 optics.
DM9301FP 100mbps ethernet fiber/twisted pair single chip media converter final 21 version: DM9301FP-ds-f03 june 06, 2007 package information 100 pins qfp package outline information: dimension in mm dimension in inch symbol min nom max min nom max a 3.40 0.134 a 1 0.25 0.010 a 2 2.73 2.85 2.97 0.107 0.112 0.117 b 0.25 0.30 0.38 0.010 0.012 0.015 c 0.13 0.15 0.23 0.005 0.006 0.009 d 23.00 23.20 23.40 0.906 0.913 0.921 d 1 19.90 20.00 20.10 0.783 0.787 0.791 e 17.00 17.20 17.40 0.669 0.677 0.685 e 1 13.90 14.00 14.10 0.547 0.551 0.555 e 0.65 bsc 0.026 bsc l 0.73 0.88 1.03 0.029 0.035 0.041 l 1 1.60 bsc 0.063 bsc y 0.10 0.004 0 o 7 o 0 o 7 o 1. dimension d 1 and e 1 do not include resin fin. 2. all dimensions are base on metric system. 3. general appearance spec should base on its final visual inspection spec.
DM9301FP 100mbps ethernet fiber/twisted pair single chip media converter 22 preliminary version: DM9301FP-ds-f03 june 06, 2007 ordering information part number pin count package DM9301FP 100 qfp (pb-free) disclaimer the information appearing in this publication is believed to be accurate. integrated circuits sold by davicom semiconductor are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. davicom makes no warranty, express, statutory, implied or by description regarding the information in this publication or regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. further, davicom makes no warranty of merchantability or fitness for any purpose. davicom reserves the right to halt production or alter the specifications and prices at any time without notice. accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. products described herein are intended for use in normal commercial applications. applications in volving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by davicom for such applications. please note that application circuits illustrated in this document are for reference purposes only. davicom?s terms and conditions printed on the order acknowledgment govern all sales by davicom. davicom will not be bound by any terms inconsistent with these unless davicom agrees otherwise in writing. acceptance of the buyer?s orders shall be based on these terms. company overview davicom semiconductor, inc. develops and manufactures integrated circuits for integration into data communication products. our mission is to design and produce ic products that are the industry?s best value for data, audio, video, and internet/intranet applications. to achieve this goal, we have built an organization that is able to develop chipsets in response to the evolving technology requirements of our customers while still delivering products that meet their cost requirements. products we offer only products that satisfy high performance requirements and which are compatible with major hardware and software standards. our currently available and soon to be released products are based on our proprietary designs and deliver high quality, high performance chipsets that comply with modem communication standards and ethernet networking standards. contact windows for additional information about davicom products, contact the sales department at: headquarters hsin-chu office: no.6 li-hsin rd. vi, science-based industrial park, hsin-chu city, taiwan, r.o.c. tel: 886-3-5798797 fax: 886-3-5646929 davicom america corp 4633 old ironsides dr., ste 318 santa clara, ca 95054, usa tel: 408.980.9108 fax:408.980.9236 warning conditions beyond those listed for the absolute maximum may destroy or damage the products. in addition, conditions for sustai ned periods at near the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and/o r function.

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